8-bit MCU (microcontroller) architecture features and design principles

1. introduction

Since the emergence of the Microcontroller in the 1970s, it has been rapidly developed and widely used in nearly 30 years. With the rapid development of microelectronics technology, microcontrollers are widely used in household appliances, computing and peripherals, communications, industrial control, automated production, and intelligent, with their outstanding performance, small size, excellent price, and complete functions. Equipment, instrumentation and other fields have become the most effective tools for scientific research, teaching, and industrial technology transformation. From the simple microcontrollers that originally used the Princeton architecture to the RISC microcontrollers that nowadays generally use the Harvard bus architecture, microcontrollers have made rapid progress.

The 8-bit microcontroller is currently the largest number of microcontrollers in use, and is currently the market where most companies are committed to cultivating; their market and price competition are extremely fierce, and the speed of various multi-functional requirements and different specifications of products is extremely fast. With the rapid development of integrated circuits and semiconductor process technologies, the continuous competition and integration of FPGA and SOC technologies, the design of electronic products is gradually getting better system performance, lower power consumption, lower cost, higher reliability, and easier development. The direction of development. Therefore, the rapid introduction of cost-effective, low-power, high-efficiency 8-bit microcontroller chips or IP Cores that meet market demands has become a hot topic for many companies today.

8-bit MCU (microcontroller) architecture features and design principles

2. Current 8-bit microcontroller update and design trends

For different microcontroller (MCU) product applications, it is necessary to consider not only the cost performance of MCUs from different manufacturers, but also the MCU application characteristics under different command systems. In response to the emerging new intelligent electronic products, people have been developing new MCU products suitable for different embedded system applications. Different manufacturers' MCU products have different instruction sets, especially the instruction set system architecture. For example, MCS51 series and PIC series microcontrollers widely used in the market use CISC instruction system and RISC instruction system respectively.

Microcontrollers can be classified into CISC, RISC, and RISC-like (RISC-LIKE) according to the instruction system. The traditional MCS51 controller is of the CISC type and has a high code density, but most instructions require multiple clock cycles to complete. RISC type general instruction density is low, but the instruction efficiency is very high. The RISC-like type combines the advantages of CISC and RISC. RISC and RISC have such high instruction efficiency, thanks to the hard-wired architecture and pipeline structure brought by the small instruction set. The simple instruction set can be decoded by hard wiring, without the need for microcode control, which improves the efficiency of decoding. The pipeline structure divides the instructions into several steps. When the pipeline is full, the average execution time (CPI) of each instruction is around 1 clock cycle. In general, RISC is 50%-70% faster than the equivalent CISC, and it is easier to design and correct errors.

Therefore, the current product development and research design for 8-bit microcontrollers is based on the premise of being compatible with products that have been widely adopted by customers in the market, continuously improving performance and reducing power consumption to adapt to market competition and technological development. For the microcontroller products originally used for the CISC command system, it has gradually merged into the RISC concept in the endless series of updates; for the microcontrollers using the RISC command system, more practices are still aimed at high performance and low power. The demand for consumption is constantly optimizing and improving the entire architecture, especially the improvement of the pipeline structure. This paper is proposed in this situation, mainly discussing the design technology of 8-bit microcontroller products of RISC architecture.

3. Structural features and design principles of RISC microprocessors

Although the industry now has different views on what features RISC processors should have, there are some commonalities in various RISC architectures: (1) Using Harvard bus architecture, most instructions are completed in one clock cycle to facilitate structural pipelining. (2) using independent and simple load/store structure; (3) instruction decoding is usually hard-wired rather than micro-decoded to speed up execution; (4) most instructions have a fixed format to simplify instruction encoding and Decoding; (5) a small instruction set and a few addressing modes; (6) data channel pipelining to make the processing highly parallel; (7) using a large-capacity high-speed register file (or register file), Try to avoid exchanging data with lower speed system RAM. Try to store the operational data in registers, thus reducing the number of accesses to memory. Based on the above discussion, the following focuses on the key technologies of 8-bit RISC microcontrollers in terms of high performance and low power consumption from the perspective of architecture.

4. Key technology

4.1 Selection of RISC instruction set

The use of the controller system is closely related to the specification interface between software programming and hardware design. This interface is the instruction set of the microcontroller. Instruction Architecture (ISA) is a prerequisite for the collaborative design of microprocessor hardware and software. The instruction set must be complete so that all computable functions are implemented in a reasonable program space; and the instruction set must be efficient so that commonly used functions can be implemented with relatively few instructions. Therefore, a microcontroller system for application development must have a complete and efficient instruction set.

The instruction set directly determines the internal hardware structure of the microcontroller, and is also the basis for the user program to compile and generate the target code. The finalization of the instruction set is closely related to and constrains the program memory, data memory, register variables, and memory addressing modes required by the entire system. Each component and even a specific byte should have a unique address so that the instruction set can correctly identify each component or byte. Therefore, there are a series of different measures for different products: 1) Weigh the length of the instruction from the required address length and the corresponding increase of the register; 2) classify the instructions and determine the various instruction bytes respectively Format to simplify the decoding logic of the operation control signal; 3) increase the corresponding register to compensate for the lack of instruction byte length; 4) the instruction byte format allocation should take into account the structural complexity of the corresponding component and the corresponding addressing mode; 5) Whether the memory, registers, and I/O ports are uniformly addressed. The above list is not exhaustive or sequential, and should be analyzed at the same time. The corresponding measures, performance, power consumption, and design complexity are different and should be considered together.

Power analysis of the ISA should be considered in terms of both instruction code size and instruction execution efficiency. The choice of techniques such as instruction set size, register variables, memory addressing modes, and pipeline structure are closely related to instruction code density. The study found that appropriately adding some specific complex instructions in RISC's reduced instruction set is a feasible way to improve code density, ensure high performance of the processor, and low power consumption. Therefore, an instruction set capable of generating high instruction code density is undoubtedly the first choice for RISC low-power design.

4.2 Pagination design of register file with shared area

The main feature of RISC design is that all operations are register-oriented. Data transfer using the register---register operation command speeds up the speed, and also simplifies the instruction control logic, reducing the chip area of ​​the control components composed of hard-wired logic.

The number of bits in the fixed register address in the instruction must limit the number of registers, but the design of the segmentation and paging of the high-end processor can extend the range of addressing. The fundamental starting point of the segmentation and paging design idea is to decompose the linear address of the memory into two-dimensional or multi-dimensional addresses; only the lowest-dimensional address is expressed in the instruction, and other facilities (such as segment number register, page number register) are used to store High dimensional address. The register file is typically divided into pages, each of which has a fixed size, and only the in-page address of the register is used in the instruction. A page number register is set in the system special register to switch access to different page registers by changing its contents.

In order to overcome various defects in the simple paging mechanism, a paging design with a shared area is usually used, which not only reduces the number of bits of the register logical address in the instruction, but also can access the system register at any time, and facilitates between different page registers. Information is exchanged through general purpose registers in the shared area. Of course, there must be a corresponding method of mapping the logical address to the physical address.

4.3 Program space paging design

For the same reason as the register file, if the full program space address is used in the instruction, the size of the program space will be limited. Therefore, the paging space design is usually adopted for the program space, and the common program area is set in different pages. (If the instruction length fully meets the requirements of the program space address, this idea is not needed), and its design idea is similar to the register paging design with the shared area, and will not be described here. The only difference from the register common area is that the program common area provides a platform for the program to jump between different pages.

4.4 Pipeline Technology

The pipeline design is inseparable from the 8-bit RISC microcontroller architecture and is the core of the design of the entire system. Its selection directly affects the performance and power consumption of the system.

Pipeline technology maximizes the use of microcontroller resources, allowing each component to work every clock cycle, greatly improving efficiency, but because of the strong dependencies between the various segments of the pipeline. If not handled properly, the operation of the instruction will not achieve the expected results, so it is necessary to be familiar with the pipeline related and transfer issues. One is resource conflict, that is, competing for the same function at the same time, generally accessing the memory at the same time, which requires a pause in the pipeline; the second is data-related conflicts, there are three types: RAW, WAR, WAW, to resolve the conflict Use the internal pass-through structure or delay the one-shot pipeline; the third is to control the transition conflict, that is, for the conditional jump instruction, according to the operation result to determine whether to jump, to determine the new PC value, the operation result is obtained after the execution phase, which makes The pipeline loses a lot of performance, and the conflict is generally solved by adding hardware to obtain the operation result in advance.

The longer the pipeline, the more serious the correlation and transfer problems: on the one hand, the complexity of the hardware control circuit is greatly increased. On the other hand, due to the pause of the pipeline tempo, the CPI value increases and the system performance decreases. Therefore, the pipeline is not as long as possible. Finding a balance between speed and efficiency is the most important.

In the pipeline design of 8-bit RISC microcontrollers, there are many options. The area, speed and power consumption of different schemes are different. The specific selection should be considered from multiple aspects. First of all, a variety of specific pipeline structure schemes and the strict timing required by the system should be derived from the system's working rate requirements and the number of pipeline stages and depths. Then, the power consumption, area, performance and pipeline-related and transfer problems caused by the system are caused. In terms of design complexity and other considerations, judge the merits and demerits of each scheme; finally, compromise the optimal scheme that meets the requirements.

4.5 Low Power Technology

With the rapid development of the semiconductor industry, integrated circuits enter the deep sub-micron stage, the clock frequency and chip integration of microprocessors continue to increase, and power consumption has become the primary concern in many design fields. The most prominent point is that High-performance microprocessors and portable electronic devices.

When the software and hardware co-design and the instruction architecture are determined according to the system function description, the design power consumption results caused by different design starting points will be very different. Therefore, the determination of the entire architecture is undoubtedly the primary problem that should be considered in the low-power problem. It mainly reflects the following aspects: 1) Optimize the instruction set according to the functional requirements as much as possible, simplify the decoding unit and execution unit of the system; 2) Develop through The parallelism of the hardware and the pipeline execution of the functional unit to realize the structure of low power consumption; 3) Reasonable setting to determine the capacity of the memory and the register, and reduce the number of buses required; 4) Different sub-module division of the system hardware and different software settings The working state is very important for power optimization.

5. Conclusion

Today, in the field of microcontroller applications, higher requirements are placed on microcontrollers, which are expected to be faster, lower in power consumption, cheaper, easier to learn and use, and fewer peripheral devices when composing systems. Therefore, product development and design research for the most widely used 8-bit microcontrollers is particularly important. And because its architecture design is the key to the entire design, all subsequent work depends on the designed architecture. This paper analyzes and discusses the issues that should be considered in the key technologies used in the 8-bit RISC architecture, which has certain research value and significance.

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