While the Cortex-M processor series is often associated with the lower end of the performance spectrum, it remains significantly more powerful than most processors found in typical microcontrollers (MCUs). For instance, the Cortex-M4 and Cortex-M7, commonly used in high-performance MCUs, can reach clock speeds of up to 400 MHz.
Of course, performance isn’t the sole consideration when selecting a processor. In many applications, factors like low power consumption and cost are equally critical. Thus, the Cortex-M family includes a variety of products catering to diverse needs (as illustrated in Table 1 below).
The Cortex-M differs from conventional ARM processors, such as ARM7TDMI and ARM9, through its extensively reengineered architecture. For one, it exclusively supports ARM Thumb instructions, which have been enhanced in Thumb-2 to include both 16-bit and 32-bit instructions.
Interrupt handling in Cortex-M processors is managed by the Nested Vectored Interrupt Controller (NVIC), which automates priority scheduling, interrupt masking, nesting configurations, and system exceptions.
Interrupt handlers can be implemented as standard C functions, leveraging a vectorized interrupt processing mechanism that eliminates the need for software-based identification of specific interrupts. This results in rapid response times and minimal latency.
In terms of the interrupt vector table, the branching instruction has been replaced with the starting addresses of the interrupt and system exception handlers. Additionally, certain aspects of the scratchpad blocks and programming modes have been adjusted.
These modifications imply that much of the combined language code written for traditional ARM processors will require revision, and legacy project files must be updated and recompiled when transitioning to Cortex-M processors.
An overview of the instruction set is essential, even if most software is written in C or higher-level languages. Understanding the instruction set supported by the Cortex-M processor helps identify which processor best suits a given task. The Instruction Set Architecture (ISA) forms part of the processor’s architecture, and Cortex-M processors can be categorized into several architectural types (see Table 2 below).
All Cortex-M processors support a Thumb instruction set. Following the introduction of Thumb-2 technology, the Thumb instruction set expanded considerably. However, different Cortex-M processors support subsets of instructions within the Thumb ISA, as depicted in Figure 1.
The Cortex-M0/M0+/M1 processor is rooted in the ARMv6-M architecture and features a compact instruction set with only 56 instructions, mostly 16 bits long, as shown in the smaller ellipse in Figure 1. Despite this, the processor handles data and scratchpad operations at 32 bits. Such a streamlined instruction set suffices for basic I/O control tasks and straightforward data processing. Given its limited instruction set, fewer logic gates are required to construct the processor—only 12,000 for the Cortex-M0 and Cortex-M0+ processors. However, some instructions lack compatibility with higher-order registers (R8-R12) and have limited capacity for dynamically generated data. This trade-off balances ultra-low-power processor design with performance.
The Cortex-M3 processor, based on the ARMv7-M architecture, supports a larger array of instructions, many of which are 32-bit, enabling more efficient utilization of high-order registers. It also incorporates vector table branching instructions, conditional execution (via IT instructions), hardware division instructions, multiply-accumulate (MAC) operations, and variable bit-field manipulations.
These advancements in the Cortex-M architecture have reshaped the landscape of embedded systems, offering developers greater flexibility and efficiency while maintaining the core principles of ARM's renowned design philosophy.
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